The present invention relates to an analog-to-digital (A/D) converter, and in particular to a serial-parallel (or sub-range type) A/D converter.
To classify an analog input into 2.sup.m an A/D converter, it is only necessary to use comparators corresponding to 2.sup.m -1 boundary values. The parallel A/D converter conforms to this concept. Since all comparators can be simultaneously operated, a high conversion speed is developed. However, as the number of bits increases, the number of comparators becomes greater, which leads to problems in that both the number of devices and the power dissipation are increased.
As an apparatus for decreasing the number of comparators required for an A/D converter, a serial-parallel A/D converter has been proposed. For example, when a desired digital signal comprises 2n bits, a course A/D conversion is first conducted on the n high-order bits, a fine A/D conversion is carried out on the n low-order bits, and then the results of the coarse and fine A/D conversion operations are combined, thereby obtaining an objective result comprising 2n bits. In this case, 2.sup.2n -1 comparators are required for a parallel A/D conversion, whereas only 2.multidot.(2.sup.n -1)=2.sup.n+1 -2 comparators are needed for a serial-parallel conversion. By increasing the number of serial stages, the number of required comparators can be further lowered. The reduction of the necessary number of compararors make it possible to decrease the number of devices and the power consumption. In the serial-parallel A/D conversion, the conversion must be repeatedly achieved as many times as there are the serial stages, and hence the conversion speed is lowered. Such a serial-parallel converter has been described, for example, in JP-A-57-131123 and 1985 IEEE International Solid-State Circuits Conference WPM 7.1 which are incorporated by reference.
For A/D converters, a differential MOS comparator and chopper MOS comparators are utilized in ordinary cases. The MOS device is characterized by a low control power, however, the differential circuit requires a constant-current power supply and the chopper circuit allows a current to flow therethrough during the autozero period. Moreover, when using a great number of comparators, the power consumed by these comparators cannot be considered to be quite low. The differential comparator and the chopper comparator have been described in the Digests of 1984 General Meeting of the Institute of Electronics and Communication Engineers of Japan, Communication Department, page 1-94, October 1984 and ISSCC 79 Digests of Technical Papers. pp. 126-127, 1979/2, respectively, which are incorporated herein by reference.